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library ieee;
use ieee.std_logic_1164.all;

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entity cmp_ts is
port(	D_in:	in std_logic;
	E: 	in std_logic;
	D_out:	out std_logic
);			  
end cmp_ts;

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architecture behv of cmp_ts is
begin
  process(D_in, E)
  begin
	if E='1' then
	  D_out <= D_in;
	else				   
	  D_out <= 'Z';
	end if;
  end process;
end behv;
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